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integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 recommended application: low power ck505 programmable clock output features: 2 - 0.8v differential push-pull cpu pairs 1 - 25 mhz 5 - pci (33mhz) 1 - usb, 48mhz 1 - 24/48mhz 1 - ref, 14.318mhz 8 - pciex 0.8v differential push-pull pairs 1 - pciex/dot96mhz selectable pairs 1 - sataclk differential pair 1 - 24.576mhz output key specifications: cpu outputs cycle-cycle jitter < 85ps pciex outputs cycle-cycle jitter < 125ps pci outputs cycle-cycle jitter < 250ps +/- 300ppm frequency accuracy on cpu & pciex clocks low power programmable timing control hub? for p 4 ? processor features/benefits: programmable output frequencies programmable output skew. programmable spread percentage for emi control. programmable watch dog safe frequency. supports tight ppm accuracy clocks for serial-ata supports spread spectrum modulation, 0.25% center spread. uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning low power differential outputs (50ohm resistor to gnd not needed) integrated 33 ? series resistor on all differential outputs advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. functionality table pin co nfiguration **rlatch 1 64 25mhz_0f_2x/freerun* gnd 2 63 gnd vdd 3 62 vdd25mhz **gsel/24.576mhz 4 61 vddsata vddpci 5 60 sataclkt_lr gnd 6 59 sataclkc_lr **doc_1 7 58 gnd pciclk0 8 57 ref0_2x/fslc pciclk1_3x 9 56 gnd fslb/pciclk2_2x 10 55 x1 selrset/reset#/pciclk3 11 54 x2 pciclk412 53vddref **doc_0 13 52 sdata vdd48 14 51 sclk fsla/usb_48mhz 15 50 gnd *sel24_48#/24_48mhz 16 49 cput_lr0 gnd 17 48 cpuc_lr0 vtt_pwrgd/wol_stop# 18 47 vddcpu dot96t_lr/pciet_lr0 19 46 cput_lr1 dot96c_lr/pciec_lr0 20 45 cpuc_lr1 gnd 21 44 vddi/o pciet_lr122 43gnda pciec_lr123 42vdda pciet_lr2 24 41 pciet_lr8 pciec_lr2 25 40 pciec_lr8 gnd 26 39 pciet_lr7 pciet_lr3 27 38 pciec_lr7 pciec_lr328 37gnd pciet_lr4 29 36 pciet_lr6 pciec_lr4 30 35 pciec_lr6 gnd 31 34 pciet_lr5 vddpciex 32 33 pciec_lr5 64-pin tssop * internal pull-up resistor ** internal pull-down resistor reset pin is 3.3v tolerant ics9lprs511 bit4 bit3 bit2 bit1 bit0 cpu pcie x pci sata fslc fslb fsla mhz mhz mhz mhz 0 0 0 0 0 266.66 100.00 33.33 100.00 0 0 0 0 1 133.33 100.00 33.33 100.00 0 0 0 1 0 200.00 100.00 33.33 100.00 0 0 0 1 1 166.66 100.00 33.33 100.00 0 0 1 0 0 333.33 100.00 33.33 100.00 0 0 1 0 1 100.00 100.00 33.33 100.00 0 0 1 1 0 400.00 100.00 33.33 100.00 0 0 1 1 1 200.00 100.00 33.33 100.00 0 1 0 0 0 266.66 100.00 33.33 100.00 0 1 0 0 1 133.33 100.00 33.33 100.00 0 1 0 1 0 200.00 100.00 33.33 100.00 0 1 0 1 1 166.66 100.00 33.33 100.00 0 1 1 0 0 333.33 100.00 33.33 100.00 0 1 1 0 1 100.00 100.00 33.33 100.00 0 1 1 1 0 400.00 100.00 33.33 100.00 0 1 1 1 1 200.00 100.00 33.33 100.00 1 0 0 0 0 269.33 101.00 33.66 100.00 1 0 0 0 1 134.66 101.00 33.66 100.00 1 0 0 1 0 202.00 101.00 33.66 100.00 1 0 0 1 1 168.33 101.00 33.66 100.00 1 0 1 0 0 274.66 103.00 34.33 100.00 1 0 1 0 1 137.33 103.00 34.33 100.00 1 0 1 1 0 206.00 103.00 34.33 100.00 1 0 1 1 1 n/a n/a 34.33 100.00 1 1 0 0 0 279.99 105.00 35.00 100.00 1 1 0 0 1 140.00 105.00 35.00 100.00 1 1 0 1 0 210.00 105.00 35.00 100.00 1 1 0 1 1 n/a n/a 35.00 100.00 1 1 1 0 0 285.33 107.00 35.66 100.00 1 1 1 0 1 142.66 107.00 35.66 100.00 1 1 1 1 0 214.00 107.00 35.66 100.00 1 1 1 1 1 n/a n/a 35.66 100.00
2 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 pin description pin# pin name t y pe pin description 1 **rlatch in asynchronous input pin used in combination with vttpwrgd signal to determine whether to reset i2c. 2 gnd pwr ground pin. 3 vdd pwr power supply, nominal 3.3v 4 **gsel/24.576mhz i/o latch input to select pciex0 and dot96 output. gsel = 1, selects dot 96mhz ; gsel = 0, selects pciex0. / 24.576mhz clock output 5 vddpci pwr power supply for pci clocks, nominal 3.3v 6 gnd pwr ground pin. 7 **doc_1 in dynamic over clocking pin: real time frequency selection 0: normal; 1: frequency will transition to a preprogrammed value in the i2c. 8 pciclk0 out pci clock output. 9 pciclk1_3x out programmable 3x strength pciclk, default 2x 10 fslb/pciclk2_2x i/o 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values. / 3.3v pci clock output. 11 selrset/reset#/pciclk3 i/o latch select input pin. selrset = 0, selects pciclk, selrset = 1 selects reset# 12 pciclk4 out pci clock output. 13 **doc_0 in dynamic over clocking pin: real time frequency selection 0: normal; 1: frequency will transition to a preprogrammed value in the i2c. 14 vdd48 pwr power pin for the 48mhz output.3.3v 15 fsla/usb_48mhz i/o 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. / fixed 48mhz usb clock output. 3.3v. 16 *sel24_48#/24_48mhz i/o latched select input for 24/48mhz output / 24/48mhz clock output. 1=24mhz, 0 = 48mhz. 17 gnd pwr ground pin. 18 vtt_pwrgd/wol_stop# in this active high 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled / asynchronous active low input pin that stops all outputs except free running 25mhz 19 dot96t_lr/pciet_lr0 out true clock of differential pair for 96.00mhz non-spreading dot clock/ true clock of pciex0 clock pair - selectable by gsel; both 0.75v differential pairs are 0.75v push- pull outputs with integrated 33ohm series resistor. 20 dot96c_lr/pciec_lr0 out complementary clock of differential pair for 96.00mhz non-spreading dot clock/ complementary clock of pciex0 clock pair - selectable by gsel; both 0.75v differential pairs are 0.75v push-pull outputs with integrated 33ohm series resistor. 21 gnd pwr ground pin. 22 pciet_lr1 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 23 pciec_lr1 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 24 pciet_lr2 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 25 pciec_lr2 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 26 gnd pwr ground pin. 27 pciet_lr3 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 28 pciec_lr3 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 29 pciet_lr4 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 30 pciec_lr4 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 31 gnd pwr ground pin. 32 vddpciex pwr power supply for pci express clocks, nominal 3.3v
3 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 pin description (continued) pin# pin name t y pe pin description 33 pciec_lr5 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 34 pciet_lr5 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 35 pciec_lr6 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 36 pciet_lr6 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 37 gnd pwr ground pin. 38 pciec_lr7 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 39 pciet_lr7 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 40 pciec_lr8 out complement clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 41 pciet_lr8 out true clock of 0.75v differential push-pull pci_express pair with integrated 33ohm series resistor 42 vdda pwr 3.3v power for the pll core. 43 gnda pwr ground pin for the pll core. 44 vddi/o pwr power supply for differential outputs 45 cpuc_lr1 out complementary clock of differential pair 0.75v push-pull cpu outputs with integrated 33ohm series resistor. 46 cput_lr1 out true clock of differential pair 0.75v push-pull cpu outputs with integrated 33ohm series resistor. 47 vddcpu pwr supply for cpu clocks, 3.3v nominal 48 cpuc_lr0 out complementary clock of differential pair 0.75v push-pull cpu outputs with integrated 33ohm series resistor. 49 cput_lr0 out true clock of differential pair 0.75v push-pull cpu outputs with integrated 33ohm series resistor. 50 gnd pwr ground pin. 51 sclk in clock pin of smbus circuitry, 5v tolerant. 52 sdata i/o data pin for smbus circuitry, 5v tolerant. 53 vddref pwr ref, xtal power supply, nominal 3.3v 54 x2 out crystal output, nominally 14.318mhz 55 x1 in crystal input, nominally 14.318mhz. 56 gnd pwr ground pin. 57 ref0_2x/fslc i/o 2x strength 14.318 mhz reference clock./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 58 gnd pwr ground pin. 59 sataclkc_lr out complement clock of 0.75v push-pull differential sata pair with integrated 33ohm series resistor. 60 sataclkt_lr out true clock of 0.75v push-pull differential sata pair with integrated 33ohm series resistor. 61 vddsata pwr supply for sata clocks, 3.3v nominal 62 vdd25mhz pwr power supply for 25mhz clocks, 3.3v nominal. 63 gnd pwr ground pin. 64 25mhz_0f_2x/freerun* i/o 2x strength 25mhz clock output, 3.3v (free running by default) / latch input to select if 25mhz_0 is freerunning or stoppable on power up default. freerun = 1, 25mhz_0 is free running, freerun = 0, 25mhz_0 is stoppable.
4 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 general description ics9lprs511 follows the intel ck505-compliant clock specification. this clock synthesizer provides a single chip solution for next generation p4 intel processors and intel chipsets. ics9lprs511 is driven with a 14.318mhz crystal. fixed pll frequency dividers pll array programmable frequency divider array stop logic 48mhz, usb x1 x2 xtal sdata sclk fsla fslb fslc vttpwrgd/wol_stop# control logic ref0 cpuclkt (1:0) cpuclkc (1:0) sataclkt sataclkc pciclk (4:0) pciext(8:1) dotclkt96/pciext0 dotclkc96/pciexc0 pciexc(8:1) 25mhz reset# doc (1:0) sel24_48# selrset 24_48mhz rlatch gsel 24.576mhz block diagram
5 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 table1: cpu pll frequency selection table b0b4 b0b3 b0b2 b0b1 b0b0 cpu pciex (b21b7 = 1) spread fslc fslb fsla mhz mhz % 0 0 0 0 0 266.66 100.00 0-0.5% down 0 0 0 0 1 133.33 100.00 0-0.5% down 0 0 0 1 0 200.00 100.00 0-0.5% down 0 0 0 1 1 166.66 100.00 0-0.5% down 0 0 1 0 0 333.33 100.00 0-0.5% down 0 0 1 0 1 100.00 100.00 0-0.5% down 0 0 1 1 0 400.00 100.00 0-0.5% down 0 0 1 1 1 200.00 100.00 0-0.5% down 0 1 0 0 0 266.66 100.00 +/-0.25% center 0 1 0 0 1 133.33 100.00 +/-0.25% cente r 0 1 0 1 0 200.00 100.00 +/-0.25% cente r 0 1 0 1 1 166.66 100.00 +/-0.25% cente r 0 1 1 0 0 333.33 100.00 +/-0.25% cente r 0 1 1 0 1 100.00 100.00 +/-0.25% cente r 0 1 1 1 0 400.00 100.00 +/-0.25% cente r 0 1 1 1 1 200.00 100.00 +/-0.25% cente r 1 0 0 0 0 269.33 101.00 +/- 0.3% center 1 0 0 0 1 134.66 101.00 +/- 0.3% center 1 0 0 1 0 202.00 101.00 +/- 0.3% center 1 0 0 1 1 168.33 101.00 +/- 0.3% center 1 0 1 0 0 274.66 103.00 +/- 0.3% center 1 0 1 0 1 137.33 103.00 +/- 0.3% center 1 0 1 1 0 206.00 103.00 +/- 0.3% center 10111 n/a n/a +/- 0.3% center 1 1 0 0 0 279.99 105.00 +/- 0.3% cente r 1 1 0 0 1 140.00 105.00 +/- 0.3% cente r 1 1 0 1 0 210.00 105.00 +/- 0.3% cente r 11011 n/a n/a +/- 0.3% cente r 1 1 1 0 0 285.33 107.00 +/- 0.3% cente r 1 1 1 0 1 142.66 107.00 +/- 0.3% cente r 1 1 1 1 0 214.00 107.00 +/- 0.3% cente r 11111 n/a n/a +/- 0.3% center
6 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 table2: pciex pll frequency selection table b19b4 b19b3 b19b2 b19b1 b19b0 pciex (b21b7 = 0) pci sata (b21b6 = 0) spread fslc fslb fsla mhz mhz mhz % 0 0 0 0 0 100.00 33.33 100.00 0-0.5% down 0 0 0 0 1 100.00 33.33 100.00 0-0.5% down 0 0 0 1 0 100.00 33.33 100.00 0-0.5% down 0 0 0 1 1 100.00 33.33 100.00 0-0.5% down 0 0 1 0 0 100.00 33.33 100.00 0-0.5% down 0 0 1 0 1 100.00 33.33 100.00 0-0.5% down 0 0 1 1 0 100.00 33.33 100.00 0-0.5% down 0 0 1 1 1 100.00 33.33 100.00 0-0.5% down 0 1 0 0 0 100.00 33.33 100.00 +/-0.25% center 0 1 0 0 1 100.00 33.33 100.00 +/-0.25% cente r 0 1 0 1 0 100.00 33.33 100.00 +/-0.25% cente r 0 1 0 1 1 100.00 33.33 100.00 +/-0.25% cente r 0 1 1 0 0 100.00 33.33 100.00 +/-0.25% cente r 0 1 1 0 1 100.00 33.33 100.00 +/-0.25% cente r 0 1 1 1 0 100.00 33.33 100.00 +/-0.25% cente r 0 1 1 1 1 100.00 33.33 100.00 +/-0.25% cente r 1 0 0 0 0 101.00 33.66 101.00 +/- 0.3% center 1 0 0 0 1 101.00 33.66 101.00 +/- 0.3% center 1 0 0 1 0 101.00 33.66 101.00 +/- 0.3% center 1 0 0 1 1 101.00 33.66 101.00 +/- 0.3% center 1 0 1 0 0 103.00 34.33 103.00 +/- 0.3% center 1 0 1 0 1 103.00 34.33 103.00 +/- 0.3% center 1 0 1 1 0 103.00 34.33 103.00 +/- 0.3% center 1 0 1 1 1 103.00 34.33 103.00 +/- 0.3% center 1 1 0 0 0 105.00 35.00 105.00 +/- 0.3% cente r 1 1 0 0 1 105.00 35.00 105.00 +/- 0.3% cente r 1 1 0 1 0 105.00 35.00 105.00 +/- 0.3% cente r 1 1 0 1 1 105.00 35.00 105.00 +/- 0.3% cente r 1 1 1 0 0 107.00 35.66 107.00 +/- 0.3% cente r 1 1 1 0 1 107.00 35.66 107.00 +/- 0.3% cente r 1 1 1 1 0 107.00 35.66 107.00 +/- 0.3% cente r 1 1 1 1 1 107.00 35.66 107.00 +/- 0.3% center
7 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 general i 2 c serial interface information for the ics9lprs511 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the beginning byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controller (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
8 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 i2c table: frequency select register byte 0 name control function type pwd a/b pwd c/d/e/h/j bit 7 rod reset on demand rw 0 0 bit 6 pciex_ss pciex pll spread enable rw 1 0 bit 5 cpu_ss cpu pll spread enable rw 1 1 bit 4 fs4 freq select bit 4 rw 0 0 bit 3 fs3 freq select bit 3 rw 0 0 bit 2 fslc freq select bit 2 rw latch latch bit 1 fslb freq select bit 1 rw latch latch bit 0 fsla freq select bit 0 rw latch latch on off on see table 1: frequency selection table 0 off 1 disable enable i2c table: frequency select register byte 1 name control function type pwd a/b/c/d/e/h/j bit 7 sel24_48 select 24_48mhz rw latch bit 6 i2c rb select i2c readback from rw 1 bit 5 selrset select reset rw latch bit 4 pciex pll mnen pciex pll m/n enable rw 0 bit 3 cpu pll mnen cpu pll m/n enable rw 0 bit 2 25mhz_0f free-running control during wol_stop rw latch bit 1 reserved reserved rw 0 bit 0 gsel gsel selection rw latch i2c table: output control register byte 2 name control function type pwd a/b/c/d/e/h/j bit 7 usb_48mhz output control rw 1 bit 6 pciext/c8 output control rw 1 bit 5 sataclk output control rw 1 bit 4 pciclk5 output control rw 1 bit 3 pciclk4 output control rw 1 bit 2 pciclk3 output control rw 1 bit 1 pciclk2 output control rw 1 bit 0 reserved reserved rw 1 i2c table: output control register byte 3 name control function type pwd a/b/c/d/e/h/j bit 7 pciclk1 output control rw 1 bit 6 pciclk0 output control rw 1 bit 5 pciext/c7 output control rw 1 bit 4 pciext/c6 output control rw 1 bit 3 pciext/c5 output control rw 1 bit 2 pciext/c4 output control rw 1 bit 1 pciext/c3 output control rw 1 bit 0 pciext/c2 output control rw 1 i2c table: output control register byte 4 name control function pwd a/b/c/d/e/h/j bit 7 pciext/c1 output control rw 1 bit 6 ref0 output control rw 1 bit 5 cpuclk1 output control rw 1 bit 4 cpuclk0 output control rw 1 bit 3 24.576mhz output control rw 1 bit 2 dot96mhz/pciext/c0 output control rw 1 bit 1 25mhz_0f output control rw 1 bit 0 reserved reserved rw 1 - 1 shadow ram active ram pciclk4 24 enable disable enable enable reset# disable disable disable disable disable enable 1 0 disable enable enable enable enable disable 1 disable 0 48 pciex0 disable disable stoppable - enable enable enable disable enable enable 0 disable disable enable disable enable - disable 01 disable disable dot96mhz disable enable enable disable enable enable free-running - disable enable - enable enable disable enable disable enable disable -
9 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 i2c table: output control register byte 5 name control function pwd a/b/c/d/e/h/j bit 7 24_48mhz output control rw 1 bit 6 diff amp rw 1 bit 5 diff amp rw 0 bit 4 reserved reserved rw 0 bit 3 iamt en (only applicable to revisions h and j, otherwise this is a reserved bit) iamt enable control rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 load control iic load control rw 0 i2c table: reserved register byte 6 name control function type pwd a/b/c/d/e/h/j bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 stoppable -- - free-running load disable enable - 0 - do not load - - - -- 01 = 900mv 10 = 800mv 11 = 700mv - 1 -- - -- - - - - - differential output amplitude control 00 = 600mv 01 i2c table: revision and vendor id register byte 7 name control function type pwd a/b pwd c/d pwd e pwd h pwd j bit 7 rid3 r 00000 bit 6 rid2 r 00111 bit 5 rid1 r 01001 bit 4 rid0 r 00010 bit 3 vid3 r 00000 bit 2 vid2 r 00000 bit 1 vid1 r 00000 bit 0 vid0 r 11111 01 - -- 001 = ics - revision id -- -- - - -- vendor id - -- i2c table: byte count register byte 8 name control function type pwd a/b/c/d/e/h/j bit 7 bc7 r 0 bit 6 bc6 r 0 bit 5 bc5 r 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 i2c table: watch dog timer control register byte 9 name control function type pwd a/b/c/d/e/h/j bit 7 hwd_en watchdog hard alarm enable rw 0 bit 6 swd_en watchdog soft alarm enable rw 0 bit 5 wd hard status wd hard alarm status r x bit 4 wd soft status wd soft alarm status r x bit 3 wdtctrl watch dog alarm time base control rw 0 bit 2 hwd2 wd hard alarm timer bit 2 rw 1 bit 1 hwd1 wd hard alarm timer bit 1 rw 1 bit 0 hwd0 wd hard alarm timer bit 0 rw 1 disable 0 writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. 1 1 0 enable normal these bits represent x*290ms (or 1.16s) the watchdog timer waits before it goes to alarm mode. default is 7 x 290ms = 2s. 1160ms base disable normal alarm byte count programming b(7:0) 290ms base enable alarm
10 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 i2c table: wd safe frequency control register byte 10 name control function type pwd a/b/c/d/e/h/j bit 7 swd2 wd soft alarm timer bit 2 rw 1 bit 6 swd1 wd soft alarm timer bit 1 rw 1 bit 5 swd0 wd soft alarm timer bit 0 rw 1 bit 4 wd sf4 rw 0 bit 3 wd sf3 rw 0 bit 2 wd sf2 rw 0 bit 1 wd sf1 rw 0 bit 0 wd sf0 rw 0 i 2 c table: cpu pll frequency control register byte 11 name control function type pwd a/b/c/d/e/h/j bit 7 n div2 n divider prog bit 2 rw x bit 6 n div1 n divider prog bit 1 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x i2c table: cpu pll frequency control register (doc0 = 0) byte 12 name control function type pwd a/b/c/d/e/h/j bit 7 n div10 rw x bit 6 n div9 rw x bit 5 n div8 rw x bit 4 n div7 rw x bit 3 n div6 rw x bit 2 n div5 rw x bit 1 n div4 rw x bit 0 n div3 rw x i2c table: cpu pll spread spectrum control register byte 13 name control function type pwd a/b/c/d/e/h/j bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x i2c table: cpu pll spread spectrum control register byte 14 name control function type pwd a/b/c/d/e/h/j bit 7 ssp15 rw 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x 1 spread spectrum programming bit(14:8) watch dog safe freq programming bits 1 0 writing to these bit will configure the safe frequency as byte10 bit (4:0). 0 1 the decimal representation of m and n divider in byte 11 and 12 will configure the cpu pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) 0 spread spectrum programming bit(7:0) these spread spectrum bits in byte 13 and 14 will program the spread percentage of cpu pll m divider programming bit (5:0) n divider programming byte12 bit(7:0) and byte11 bit(7:6) 1 1 these bits represent x*290ms (or 1.16s) the watchdog timer waits before it goes to alarm mode. default is 7 x 290ms = 2s. these spread spectrum bits in byte 13 and 14 will program the spread percentage of cpu pll 0 the decimal representation of m and n divider in byte 11 and 12 will configure the cpu pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) 0
11 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 i2c table: pciex pll frequency control register byte 15 name control function type pwd a/b/c/d/e/h/j bit 7 n div2 n divider prog bit 2 rw x bit 6 n div1 n divider prog bit 1 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x i2c table: pciex pll frequency control register (doc0 = 0) byte 16 name control function type pwd a/b/c/d/e/h/j bit 7 n div10 rw x bit 6 n div9 rw x bit 5 n div8 rw x bit 4 n div7 rw x bit 3 n div6 rw x bit 2 n div5 rw x bit 1 n div4 rw x bit 0 n div3 rw x i2c table: pciex pll spread spectrum control register byte 17 name control function type pwd a/b/c/d/e/h/j bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x i2c table: pciex pll spread spectrum control register byte 18 name control function type pwd a/b/c/d/e/h/j bit 7 ssp15 rw 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x i2c table: pciex pll frequency select register byte 19 name control function type pwd a/b/c/d/e/h/j bit 7 reserved reserved rw 1 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 fs4 freq select bit 4 rw 0 bit 3 fs3 freq select bit 3 rw 0 bit 2 fslc freq select bit 2 rw latch bit 1 fslb freq select bit 1 rw latch bit 0 fsla freq select bit 0 rw latch - m divider programming bit (5:0) 1 - n divider programming byte16 bit(7:0) and byte15 bit(7:6) the decimal representation of m and n divider in byte 15 and 16 will configure the pciex pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) the decimal representation of m and n divider in byte 15 and 16 will configure the pciex pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) see table 2: pciex pll frequency selection table spread spectrum programming bit(7:0) 1 0 - -- 0 01 these spread spectrum bits in byte 17 and 18 will program the spread percentage of pciex pll 01 0 1 - spread spectrum programming bit(14:8) these spread spectrum bits in byte 17 and 18 will program the spread percentage of pciex pll
12 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 i2c table: output control register byte 20 name control function type pwd a/b/c/d/e/h/j bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 pciex pll tben pciex pll turbo enable rw 0 bit 2 cpu pll tben cpu pll turbo enable rw 0 bit 1 reserved reserved rw 0 bit 0 reset sync reset synchronization upon reset (byte 21) rw 0 disable - - - - 01 -- - - enable enable - disable enable disable - i2c table: synchronization control register byte 21 name control function type pwd a/b pwd c/d/e/h pwd j bit 7 pciex source pciex source rw 0 1 0 bit 6 sata source sata source rw 1 1 1 bit 5 reserved reserved rw 1 1 1 bit 4 reserved reserved rw 1 1 1 bit 3 reserved reserved rw 1 1 1 bit 2 reserved reserved rw 1 1 1 bit 1 reserved reserved rw 1 1 1 bit 0 reserved reserved rw 1 1 1 - 01 - -- - - cpu pll pciex pll pciex pll - fixed pll - - - - - i2c table: doc pin control register byte 22 name control function type pwd a/b/c/d/e/h/j bit 7 pciex pciex pll doc0 pin control rw 1 bit 6 cpu cpu pll doc0 pin control rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 1 bit 0 reserved reserved rw 1 i2c table: cpu pll doc 1 n programming register (doc0 = 1) byte 23 name control function type pwd a/b/c/d/e/h/j bit 7 n div10 rw x bit 6 n div9 rw x bit 5 n div8 rw x bit 4 n div7 rw x bit 3 n div6 rw x bit 2 n div5 rw x bit 1 n div4 rw x bit 0 n div3 rw x bytes 24 and 25 are reserved i2c table: pciex pll doc 1 n programming register (doc0 = 1) byte 26 name control function type pwd a/b/c/d/e/h/j bit 7 n div10 rw x bit 6 n div9 rw x bit 5 n div8 rw x bit 4 n div7 rw x bit 3 n div6 rw x bit 2 n div5 rw x bit 1 n div4 rw x bit 0 n div3 rw x 01 n divider programming byte26 bit(7:0) and byte15 bit(7:6) the decimal representation of m and n divider in byte 15 and 26 will configure the pciex pll vco frequency. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) 01 n divider programming byte23 bit(7:0) and byte11 bit(7:6) the decimal representation of m and n divider in byte 11 and 23 will configure the cpu pll vco frequency. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) -- -- -- -- -- -- 01 enabled dis abled enabled dis abled
13 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 i2c table: programmable output divider register byte 29 name control function type pwd a/b/c/d/e/h/j bit 7 cpudiv3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 6 cpudiv2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 5 cpudiv1 rw 0010:/5 0110:/10 1010:/20 1110:/20 x bit 4 cpudiv0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x bit 3 pciexdiv3 rw 0000:/2 0100:/4 1000:/8 1100:/10 x bit 2 pciexdiv2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 pciexdiv1 rw 0010:/5 0110:/10 1010:/20 1110:/20 x bit 0 pciexdiv0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x i2c table: programmable output divider register byte 30 name control function type pwd a/b/c/d/e/h/j bit 7 pciexdiv3 rw 0000:/5 0100:/10 1000:/20 1100:/40 x bit 6 pciexdiv2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 5 pciexdiv1 rw 0010:/n/a 0110:/n/a 1010:/n/a 1110:/n/a x bit 4 pciexdiv0 rw 0011:/n/a 0111:/n/a 1011:/n/a 1111:/n/a x bit 3 pcidiv3 rw 0000:/n/a 0100:/n/a 1000:/n/a 1100:/n/a x bit 2 pcidiv2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 pcidiv1 rw 0010:/9 0110:/18 1010:/36 1110:/72 x bit 0 pcidiv0 rw 0011:/n/a 0111:/n/a 1011:/n/a 1111:/n/a x i2c table: strength control register byte 31 name control function type pwd a/b/c/d/e/h/j bit 7 25str_1 rw 1 bit 6 25str_0 rw 1 bit 5 refstr_1 rw 1 bit 4 refstr_0 rw 1 bit 3 pcistr_1 rw 0 bit 2 pcistr_0 rw 1 bit 1 pcistr_1 rw 1 bit 0 pcistr_0 rw 1 i2c table: skew programming register byte 32 name control function type pwd a/b/c/d/e/h/j bit 7 cpuskw3 rw 0000:0 0100:400 1000:800 1100:1200 0 bit 6 cpuskw2 rw 0001:100 0101:500 1001:900 1101:1300 0 bit 5 cpuskw1 rw 0010:200 0110:600 1010:1000 1110:1400 0 bit 4 cpuskw0 rw 0011:300 0111:700 1011:1100 1111:1500 0 bit 3 cpuskw3 rw 0000:0 0100:400 1000:800 1100:1200 0 bit 2 cpuskw2 rw 0001:100 0101:500 1001:900 1101:1300 0 bit 1 cpuskw1 rw 0010:200 0110:600 1010:1000 1110:1400 0 bit 0 cpuskw0 rw 0011:300 0111:700 1011:1100 1111:1500 0 cpuclk1 skew control (ps) cpu divider ratio programming bits pciex divider ratio programming bits for cpu pll pciex divider ratio programming bits for pciex pll pci divider ratio programming bits cpuclk0 skew control (ps) refclk0 strength control pciclk1 strength control pciclk2 strength control 25mhz_0 strength control 1 0 01 01 01 00 = tristated b y tes 27 and 28 are reserved 10 = 1.00x 01 = 0.1x 11 = 2.00x 00 = tristated 10 = 1.00x 00 = tristated 10 = 1.00x 01 = 0.1x 11 = 2.00x 01 = 0.1x 11 = 2.00x 01 = 2.00x 11 = 3.00x 00 = tristated 10 = 1.00x
14 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 electrical characteristics - input/supply/common output parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c 1 supply voltage vddxxx supply voltage 3.135 3.465 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 1.05 3.465 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v ols e single-ended outputs, i ol = 1 ma 0.4 v 1 output high voltage v ohdif differential outputs, i oh = tbd ma 0.7 0.9 v 1 output low voltage v oldi f differential outputs, i ol = tbd ma 0.4 v 1 low threshold input- high voltage (test mode) v ih_fs_test 3.3 v +/-5% 2 v dd + 0.3 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 i dd_default 3.3v supply, pll3 off tbd ma 1 i dd_pll3dif 3.3v supply, pll3 differential out tbd ma 1 i dd_pll3se 3.3v supply, pll3 single-ended out tbd ma 1 i dd_io 0.8v supply, differential io current, all outputs enabled tbd ma 1 i dd_pd3.3 3.3v supply, power down mode tbd ma 1 i dd_pdio 0.8v io supply, power down mode tbd ma 1 i dd_iamt3.3 3.3v supply, iamt mode tbd ma 1 i dd_iamt0.8 0.8v io supply, iamtmode tbd ma 1 input frequency f i v dd = 3.3 v tbd mhz 2 pin inductance l p in 7nh1 c in logic inputs 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 c inx x1 & x2 pins tbd pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 operating supply current power down current iamt mode current input capacitance absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 1,7 maximum supply voltage vddxxx_io low-voltage differential i/o supply 3.8 v 1,7 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,7,8 minimum input voltage v il any input gnd - 0.5 v 1,7 storage temperature ts - -65 150 c 1,7 case temperature tcase - 115 c 1 input esd protection esd prot human body model 2000 v 1,7
15 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 ac electrical characteristics - input/common parameters parameter symbol conditions min max units notes clk stabiliz ation t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after pci_stop# de-assertion 15 ns 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1 tfall_pd# t fall 5ns1 trise_pd# t rise 5ns1 fall/rise time of pd#, pci_stop# and cpu_stop# inputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 2.5 8 v/ns 1,2 falling edge slew rate t flr differential measurement 2.5 8 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpu skew20 differential measurement 150 ps 1 src[10:0] skew src skew differential measurement tbd ps 1 ac electrical characteristics - (cpu, pciex, sataclk, dot96mhz) low power differential outputs
16 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,6 33.33mhz output nominal 30.00900 ns 6 33.33mhz output spread 30.15980 ns 6 absolute min/max period t abs 33.33mhz output nominal/spread 29.49100 30.65980 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t skew v t = 1.5 v 250 ps 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 clock period 29.99100 t period output high current i oh output low current i ol electrical characteristics - usb48mhz, 24_48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 48.00mhz output nominal 20.83125 20.83542 ns 2 absolute min/max period t abs 48.00mhz output nominal 20.48130 21.18540 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 1 output high current i oh i ol output low current electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ols m b @ i pullup 0.4 v 1 current sinking at v ols m b = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1
17 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8203 69.8622 ns 2 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# falling) 6 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#. the average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 7 operation under these conditions is neither implied, nor guaranteed. 8 maximum input voltage is not to exceed maximum vdd
18 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 ics9lprs511 y glf-t example: designation for tape and reel packaging rohs compliant (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t index area 12 n d e1 e seating plane a1 a a2 e -c- b c l aaa c min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.170.27.007.011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.450.75.018.030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 ordering information
19 integrated circuit systems, inc. ics9lprs511 advance information 1137?09/05/08 silicon revision history rev. description 0.1 b0b6 = 1 in revisions [a:b] b0b6 = 0 in revisions [c:j] 0.2 b7 = 01h in revisions [a:b] b7 = 21h in revisions [c:d] b7 = 41h in revision e b7 = 51h in revision h b7 = 61h in revision j 0.3 b21b7 = 0 in revisions [a:b] b21b7 = 1 in revisions [c:h] b21b7 = 0 in revision j revision history rev. issue date description page # 0.1 8/3/2005 initial release - 0.2 8/17/2005 updated pinout and invert vttpwrgd/wol_stop polarity 1-4 0.3 8/25/2005 added i2c tables 8-21 0.4 8/31/2005 updated pinout (doc1 removed, pciclk1 added) 1-3, 19-21 0.5 9/19/2005 1) updated pinout, pin description (move freerun latch from pciclk to 25mhz_0) 2) updated i2c b y tes 1, 5, 22, 31 1-3, 8-18 0.6 10/6/2005 1) changed pin 42, 53, 61 and 62 from standby (non collapsible) power to standard power. 2) removed power groups table. 1,3, 4 0.7 4/7/2006 updated i2c. 8-18 0.5 7/31/2006 1. updated pinout. 2. updated pin description. 1,2 0.6 9/26/2006 1. updated i2c. 8-13 0.7 11/2/2006 1. updated output features to represent low power. 2. updated i2c. various 0.8 10/4/2007 updated functionality and cpu frequency table 1, 5 0.9 9/5/2008 added case temperature @ 115c to max rating table. 14 this product is protected by united states patent no. 7,342,420 and other patents.

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